Several standards have emerged for a high-speed serial communication including PCI-Express, Infiniband and XAUI. The XAUI interface is defined by IEEE standard 802.3ae for chip-to-chip or computer-to-computer communication using a 10 Gigabit Ethernet connection. XAUI allows for a low-pin-count electrical interface called a “data link” that includes four differential channels or “lanes” that couple a transmitter on one chip or computer to a receiver on another chip or computer. FIG. 1 shows an example data link 102 coupling together two computers 104, 106 that allows for high-speed communication between the computers using a XAUI interface. FIG. 2 shows an example of a printed circuit board 200 with ASICs 202, 204, each of which houses the necessary hardware for a XAUI interface shown generally at 206, 208. A data link 210 connects the XAUI interfaces 206, 208 together to allow serial communication there between.
Both PCI-Express and Infiniband have link training mechanisms wherein the transmitter uniquely identifies each lane and the receiver uses this identification to arrange the lanes in the correct order. The link training is necessary for PCI-Express and Infiniband, because those standards allow for links of various widths. This allows a user to arbitrarily choose how to connect the transmitter lanes to the receiver lanes. As a result, the user can choose an optimum printed circuit board layout without the constraint of having to connect a particular lane of the transmitter to a particular lane of the receiver.
FIG. 3 shows a block diagram of a PCI-Express or Infiniband transmitter 300. Data to be transmitted over a data link is received on input channel 302. Control characters may be inserted into the data, as shown at 304. The data is encoded (306), serialized (308), and then transmitted on output lanes shown generally at 310. Link training block 312 operates when the link is initialized and transmits special codes on each lane that uniquely identify the lane of the transmitter.
FIG. 4 shows a PCI-Express or Infiniband receiver 400. The lanes 310 from the transmitter are received on input lanes 402. The data on the input lines is de-serialized (404), decoded (406) and de-skewed (408). The receiver 400 also includes link training 410 and a lane reorderer 412. The link training block 410 is responsible for determining the identity of each lane by detecting the special codes sent by the transmitter and configuring the lane reorderer 412 to correctly sequence the lanes. Thus, it is not necessary to connect any particular lane of the transmitter to a particular lane of the receiver as the link training protocol that operates at initialization identifies the lanes so the receiver reorders the lanes appropriately. After the lanes are reordered, the control character removal block 414 removes any control characters and the data is output on port 416.
Unfortunately, the XAUI interface for the 10 Gb Ethernet does not have an equivalent training and identification scheme that allows automatic detection and arrangement of lanes within a XAUI link. FIG. 5 shows the XAUI link relative to other layers in an OSI layer model. XAUI is a part of the optional XGMII extender 500 that includes XGXS blocks 502, 504. FIG. 6 shows further structure of the XGXS blocks 502, 504 of FIG. 5. Each XGXS block includes a transmit-and-receive pair that allow for full-duplex communication. For example, a XAUI transmitter 602 within XGXS block 502 is coupled to a XAUI receiver 604 in XGXS block 504. Likewise transmitter 606 in XGXS block 504 is coupled to the XAUI receiver 608 in XGXS block 502.
FIG. 7 shows further detail of the XAUI transmitter 606 and the XAUI receiver 608. The XAUI transmitter takes a 32-bit data bus (D 31:0) and four control lines (C 3:0) and converts them into four separate transmit lanes shown generally at 700. The XAUI receiver takes the four separate transmit lanes 700 and reconstitutes the original 32-bit data bus and four control lines to generate an output shown generally at 702.
FIG. 8 shows a more detailed block diagram of the XAUI transmitter 606. A parallel data bus of 32 bits is received on input port 802 and is converted to four serial lanes operating at 3.125 Gbps shown generally at 804. Each lane has an encoder, shown generally at 806, and a serializer, shown generally at 808, associated therewith. Additionally a control character insertion block 810 is used to insert control characters into the data stream to support various features well understood in the art.
FIG. 9 shows a prior art XAUI receiver 608 in greater detail. The serial output 804 from the transmitter (FIG. 8) is received on input port 902. Each lane is then de-serialized (904), decoded (906), and de-skewed (908). Finally, the control character removal block 910 removes the characters previously inserted by the transmitter and outputs the final data on output port 912.
Notably, the XAUI transmitter and receiver do not have any provision to automatically detect lane numbers. Thus, a designer must ensure that lane 0 of the transmitter is connected correctly to lane 0 of the receiver and likewise for lanes 1, 2 and 3. Thus, there is a need for automatic lane detection in a XAUI interface.